@article {10.3844/ajeassp.2010.189.192,
article_type = {journal},
title = {A Novel Low-Power CMOS Operational Amplifier with High Slew Rate and High Common-Mode Rejection Ratio},
author = {Nabhan, Ismail and Abdallah, Moussa},
volume = {3},
number = {1},
year = {2010},
month = {Mar},
pages = {189-192},
doi = {10.3844/ajeassp.2010.189.192},
url = {https://thescipub.com/abstract/ajeassp.2010.189.192},
abstract = {Problem statement: High speed operational amplifier is always an on-going research topic since major high speed application are needed. Approach: A two-stage operational amplifier (op amp) is designed, simulated and fabricated using a UMC 0.5 μm 2P2M CMOS technology. Results: This chip includes a compensation technique to ensure stability and zero systematic input-offset-voltage. The fabricated chip achieves a 84 dB open loop gain, a 24 V μS-1 slew rate, a 84 dB CMRR utilizing a capacitive load of 5 pF, a 30 MHz unity gain frequency and consumes 2.8 mW from a 2.5 V power supply. Conclusion: The proposed chip, which is the first available CMOS operational amplifier in Jordan as the authors are aware, is well-suited to low-voltage applications since it does not require cascade output stages.},
journal = {American Journal of Engineering and Applied Sciences},
publisher = {Science Publications}
}