Efficient Realization of S-Box based reduced Residue of Prime Numbers using Virtex-5 and Virtex-6 FPGAs
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Copyright: © 2020 Mohammed H. Al Mijalli. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
Problem statement: The S-Box transformation is a computationally intensive and important operation of the Advanced Encryption Standard (AES). Approach: This study presents the comparative study between reduced Residue of Prime Numbers and Galois Filed GF (28) based SBoxes using Virtex-5 and Virtex-6 FPGA devices. The implementation of S-Boxes is done using Very High speed integrated circuit Hardware Description Language (VHDL). Results: The results obtained from Virtex-6 FPGA show that the proposed method runs at a clock frequency of 0.785ns, which is three times faster than S-Box based on Galois Filed GF (28). Conclusion: The reduced version of the S-Box based on prime number shows promising results as compared to Galois Field GF (28) based SBox, which could be used in AES to increase its complexity and add more confusion.
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- Advanced Encryption Standard (AES)
- Field Programmable Gate Array (FPGA)
- Galois Field GF (28)
- reduced residue of prime number