Research Article Open Access

A Novel Method for Testing Digital to Analog Converter in Static Range

K. Hariharan1, S. Gouthamraj1, B. Subramaniam1, S. R.V. Babu1 and V. Abhaikumar1
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American Journal of Applied Sciences
Volume 7 No. 8, 2010, 1157-1163

DOI: https://doi.org/10.3844/ajassp.2010.1157.1163

Submitted On: 14 August 2010 Published On: 31 August 2010

How to Cite: Hariharan, K., Gouthamraj, S., Subramaniam, B., Babu, S. R. & Abhaikumar, V. (2010). A Novel Method for Testing Digital to Analog Converter in Static Range. American Journal of Applied Sciences, 7(8), 1157-1163. https://doi.org/10.3844/ajassp.2010.1157.1163

Abstract

Problem statement: Linearity testing methods for DAC usually involves usage of non-linear analog components, which are indeed prone to various errors. Few other testing methodologies involve complex circuitry for measuring exactitude of DAC. Practically, it is difficult to build those as Built In Self Test (BIST) due to complexity of calculation, which demands more usage of ALU (or core of processing unit). This research aims to optimize and simplify the design of DAC testing scheme, while minimizing the computational overhead. Henceforth, the testing technique can be brought on to BIST level circuitry. Approach: A slope generator (more commonly known as integrator) produces a Ramp type of output voltage when it is fed with a DC voltage, slope of ramp depends upon the magnitude of DC-voltage. These varying slopes, when converted into a useful number, can provide some information, regarding voltage level of input. Results: In this research, we replace the DC input of the Slope generator by analog output of DAC, which is under test. As the output of DAC varies according to the Digital code input, various slopes can be generated. These slopes are converted here into useful numbers called tick counts, by measuring the time taken by Ramp type output to cross a defined threshold voltage interval. The proposed method makes use of an integrator to produce a ramp signal of high precision and conditioned slope. The actual slope produced by the output of the DAC is compared with the expected slope by counting the number of clock ticks. Conclusion: This system of using Time Tick based BIST eludes the usage of high precision non-linear devices like ADCs to test DACs. Also this system reduces exigency of separate ALU for computing error.

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Keywords

  • Time Tick BIST
  • DNL
  • INL
  • DAC error testing
  • DAC Performance evaluation