Research Article Open Access

A Novel High-Speed 54⨯54 bit Multiplier

Pouya Asadi1 and Keivan Navi1
  • 1 ,
American Journal of Applied Sciences
Volume 4 No. 9, 2007, 666-672

DOI: https://doi.org/10.3844/ajassp.2007.666.672

Submitted On: 24 March 2007 Published On: 30 September 2007

How to Cite: Asadi, P. & Navi, K. (2007). A Novel High-Speed 54⨯54 bit Multiplier. American Journal of Applied Sciences, 4(9), 666-672. https://doi.org/10.3844/ajassp.2007.666.672

Abstract

A new 54⨯54-bit multiplier using high-speed carry-lookahead adder has been fabricated by CMOS technology. This paper presents a self-timed carry-lookahead adder in which the logic complexity was a linear function of n, the number of inputs, and the average computation time was proportional to the logarithm of the logarithm of n. To the best of our knowledge, our adder has the best area-time efficiency. A novel 4-2 compressor, featuring pass-transistor multiplexers, has been developed. The proposed circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages was minimized due to the high logic functionality of passtransistor multiplexers. The total number of transistors of the proposed multiplier core was 42579 and The multiplication time was 3.4 ns at a 1.3 V power supply.

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Keywords

  • Adder
  • booth encoder
  • compressor
  • CMOS