Journal of Computer Science

LOW POWER ANALOG MULTIPLIER USING MIFGMOS

K. Duraisamy, U. Ragavendran, Wathita Phachonpai, Supaporn Muchimapura, Terdthai Tong-Un, Jintanaporn Wattanathorn and Wipawee Thukhammee

DOI : 10.3844/jcssp.2013.514.520

Journal of Computer Science

Volume 9, Issue 4

Pages 514-520

Abstract

A novel 4-quadrant analog multiplier using Floating Gate MOS (FGMOS) transistors operating in saturation region are implemented. Floating gate MOSFETs are being utilized in a number of new and existing analog applications. These devices are not only useful for designing memory elements but also we can implement circuit elements. The main advantage in FGMOS is that the drain current is proportional to square of the weighted sum of input signals. By using conventional transistors we obtain only few hundred mill volts range of the supply voltage and when we go for square law devices we obtain up to 50%. So in order to get 100% range of the supply voltage we go for FGMOS. This can be obtained by the control voltage applied at the gate of the FGMOS. This simulation is done with the SPICE tools.

Copyright

© 2013 K. Duraisamy, U. Ragavendran, Wathita Phachonpai, Supaporn Muchimapura, Terdthai Tong-Un, Jintanaporn Wattanathorn and Wipawee Thukhammee. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.