Braun's Multipliers: Spartan-3AN based Design and Implementation
Muhammad H. Rais and Mohammed H. Al Mijalli
DOI : 10.3844/jcssp.2011.1629.1632
Journal of Computer Science
Volume 7, Issue 11
Problem statement: Multiplication is an essential airthematic operation for common Digital Signal Processing (DSP) applications, such as filtering and Fast Fourier Transform (FFT). To achieve high execution speed, parallel array multipliers are widely used. Approach: The field Programmable Gate Arrays (FPGAs) is currently the dominant and viable technology that could be implemented and reconfigured at the same time. Results: The Sparatn-3An FPGA resources utilization for 4×4, 6×6, 8×8 and 12×12 bit Braun’s multipliers are obtained and Analysis Of Variance (ANOVA) presents that the 12×12 multiplier has significant difference than other three multipliers. The mean delay time for four multipliers shows that as the size of multiplier increases the mean delay time also increases. Conclusion: In essence, parallel multipliers based on the FPGA technology can provide better solution for DSP processor, medical imaging and multimedia.
© 2011 Muhammad H. Rais and Mohammed H. Al Mijalli. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.