Journal of Computer Science

Low Power Multiplier Design Using Latches and Flip-Flops

C. N. Marimuthu and P. Thangaraj

DOI : 10.3844/jcssp.2010.1117.1122

Journal of Computer Science

Volume 6, Issue 10

Pages 1117-1122

Abstract

Problem statement: Power dissipation is designated as critical parameter in modern VLSI design field. In VLSI implementation low power concept is necessary to meet Moore’s law and to produce consumer electronics with more back up and less weight. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power which is the major part of power dissipation. Multiplication occurs frequently finite impulse response filters, fast Fourier transforms, discrete cosine transform and other important DSP and multimedia kernels. Being one among the functional components of many digital systems the reduction of power dissipation in multipliers should be as much as possible. Approach: In this study a low power structure called Bypass Zero Feed A Directly (BZFAD) for shift and add multipliers was proposed for reducing the switching activity. Results: The simulation results showed conventional and proposed BZFAD 8 bit multipliers. Conclusion: From these results, BZFAD can attain considerable power reduction and area saving when compared to the conventional shift and add multipliers.

Copyright

© 2010 C. N. Marimuthu and P. Thangaraj. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.