Study of Network on Chip resources allocation for QoS Management
Abdelhamid HELALI, Adel SOUDANI, Jamila BHAR and Salem NASRI
DOI : 10.3844/jcssp.2006.770.774
Journal of Computer Science
Volume 2, Issue 10
The increasing complexity of integrated circuits and application requirements drive the research of new on-chip interconnection architectures. A network on chip draws on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. The main goal pursued is to achieve superior bandwidth when compared to conventional on-chip bus architectures. The complexity of Systems-on-Chip (SoC) is growing; meeting real-time requirements is becoming increasingly difficult. Predictability for computation, memory and communication components are needed to build up real-time SoC. To achieve guaranteed throughput and bounded delivery delay, buffers in network interfaces (NIs) must be dimensioned to hide round-trip latency and rate difference between computation and IPs communication.. It is crucial to shape these buffers according to the network requirements and to bring out the right specification before the design step to provide desired performances in the SoC. In this field this paper describes and presents a performance analyses of NoC shaped on mesh architecture. The goal of this work is to quantify buffering requirements in the NoC nodes by the analyze of some QoS metrics such as drop, compute latency, and throughput. This study presented in this paper is based on simulation approach of a mesh (4 x 4 ) NoC behavior under multimedia communication process with MPEG-4 (Moving Picture Experts Group) flows.
© 2006 Abdelhamid HELALI, Adel SOUDANI, Jamila BHAR and Salem NASRI. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.