Journal of Computer Science

Asynchronous NoC Router Design

Sami Badrouchi, Abdelkrim Zitouni, Kholdoun Torki and Rached Tourki

DOI : 10.3844/jcssp.2005.429.436

Journal of Computer Science

Volume 1, Issue 3

Pages 429-436

Abstract

The Quality of Service Network on Chip (QNoC) is the most perferment solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents an asynchronous NoC router, for use in 2-D mesh-connected networks. It comprises multiple interconnected input and output ports and dynamic arbitration mechanisms that resolve any output port conflicts based on the messages priorities. The proposed router protocol and its asynchronous modeling are based on the Speed Independent State Transition Graph (STG) model. The generated STG are transformed into VHDL data flow descriptions and the low level implementation is based onto a parameterized library. This library integrates the popular asynchronous SI modules such as C-element, Q-element, fairly arbiter, etc. The device is implemented in 0.35 µm CMOS technology and its performance is compared with a synchronous router of the same functionality. The asynchronous router enables a higher data rate and a comparable silicon area.

Copyright

© 2005 Sami Badrouchi, Abdelkrim Zitouni, Kholdoun Torki and Rached Tourki. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.