American Journal of Engineering and Applied Sciences

Low Power Multiplier by Effective Capacitance Reduction

Nageshwar Reddy Peddamgari and Damu Radhakrishnan

DOI : 10.3844/ajeassp.2017.126.133

American Journal of Engineering and Applied Sciences

Volume 10, Issue 1

Pages 126-133

Abstract

In this study we present an energy efficient multiplier design based on effective capacitance minimization. Only the partial product reduction stage in the multiplier is considered in this research. The effective capacitance at a node is defined as the product of capacitance and switching activity at that node. Hence to minimize the effective capacitance, we decided to ensure that the switching activity of nodes with higher capacitance is kept to a minimum. This is achieved by wiring the higher switching activity signals to nodes with lower capacitance and vice versa, for the 4:2 compressor and adder cells. This reduced the overall switching capacitance, thereby reducing the total power consumption of the multiplier. Power analysis was done by synthesizing our design on Spartan-3E FPGA. The dynamic power for our 1616 multiplier was measured as 360.74 mW and the total power 443.31 mW. This is 17.4% less compared to the most recent design. Also, we noticed that our design has the lowest power-delay product compared to the multipliers presented in literature.

Copyright

© 2017 Nageshwar Reddy Peddamgari and Damu Radhakrishnan. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.