PERFORMANCE ANALYSIS OF HIGH EFFICIENCY LOW DENSITY PARITY-CHECK CODE DECODER FOR LOW POWER APPLICATIONS
M. Revathy and R. Saravanan
DOI : 10.3844/ajassp.2014.558.563
American Journal of Applied Sciences
Volume 11, Issue 4
In this study, we propose a low power, high efficient Low Density Parity-Check Code (LDPC) Decoder Architecture for error detection and correction applications. LDPC codes have been adopted in latest wireless standards such as satellite and mobile communications since they possess superior error-detecting and correcting capabilities. As technology scales, memory devices become larger and more powerful and low power consumption based error correction codes are needed. This study discuses the design and analysis of check node unit and variable node unit in LDPC decoder. The architecture is synthesized on Xilinx 9.2i and simulated using Modelsim, which is targeted to 90 nm device. Synthesis report shows that the proposed architecture reduces the hardware utilization and power consumption when compared to the conventional architecture design.
© 2014 M. Revathy and R. Saravanan. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.