FPGA IMPLEMENTATION AND ANALYSIS OF IMPULSE NOISE REDUCTION IN IMAGES
- 1 Department of Electronics and Communication, PSNA College of Engineering and Technology, Tamil Nadu- 624622, India
- 2 Department of Electronics and Communication, RMD Engineering College, India
- 3 Department of Electronics and Communication, RMK Engineering College, India
Abstract
The images are affected by random valued impulse noises during the image capturing and processing stages. In this study, an efficient, high performance and low hardware utilized impulse noise reduction algorithm is presented. This methodology determines the optimum direction pixels through the estimation of standard deviation. The edges in the images are preserved during the process of impulse noise detection and removal stage. The hardware architecture for this design is proposed and its performance is analyzed with different FPGA Processors in terms of slices, LUTs and power consumption. The proposed hardware architecture consumes 1728 gates and power consumption of 159.95 mW. The main motivation behind this research is to design low power impulse noise detection architecture and its real time implementations.
DOI: https://doi.org/10.3844/ajassp.2014.1041.1048
Copyright: © 2014 P. Thirumurugan, S. Sasikumar and C. Sugapriya. This is an open access article distributed under the terms of the
Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
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Keywords
- Impulse Noise Reduction
- Optimal Detector
- Power Consumption
- Edge Detection
- Image Quality