Spartan-3AN Field Programmable Gate Arrays Truncated Multipliers Delay Study
Mohammed H. Al Mijalli
DOI : 10.3844/ajassp.2011.554.557
American Journal of Applied Sciences
Volume 8, Issue 6
Problem statement: The image processing applications, such as MPEG video compression used in CT scan frames requires real time conditions and the algorithms should be verified and optimized before implementation which cannot be done with Application Specific Integrated Circuits (ASICs) because they are not reconfigurable and cost is very high. Approach: The FPGA is a viable technology that could be implemented and reconfigured at the same time, since FPGA have the benefit of hardware speed and the flexibility of software. Results: The results obtained from Sparatn-3An FPGA show that the mean delay time for four multipliers, clearly indicates as the size of multiplier increases the mean delay time also increases. Conclusion: The FPGA based truncated multipliers could also be used in medical imaging technology.
© 2011 Mohammed H. Al Mijalli. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.