American Journal of Applied Sciences

Reconfigurable Elliptic Curve Crypto-Hardware Over the Galois Field GF(2163)

Mohamed Abdelkader Bencherif, Hamid Bessalah and Abderrezak Guessoum

DOI : 10.3844/ajassp.2009.1596.1603

American Journal of Applied Sciences

Volume 6, Issue 8

Pages 1596-1603


Problem statement: In the last decade, many hardware designs of elliptic curves cryptography have been developed, aiming to accelerate the scalar multiplication process, mainly those based on the Field Programmable Gate Arrays (FPGA), the major issue concerned the ability of embedding this strategic and strong algorithm in a very few hardware. That is, finding an optimal solution to the one to many problem: Portability against power consumption, speed against area and maintaining security at its highest level. Our strategy is to hardware execute the ECC algorithm that reposes on the ability of making the scalar multiplication over the GF(2163) in a restricted number of clock cycles, targeting the acceleration of the basic field operations, mainly the multiplication and the inverse process, under the constraint of hardware optimization. Approach: The research was based on using the efficient Montgomery add and double algorithm, the Karatsuba-Offman multiplier and the Itoh-Tsjuii algorithm for the inverse component. The hardware implementation was based upon an optimized Finite State Machine (FSM), with a single cycle 163 bits multiplier and a script generated field squarer. The main characteristics of the design concerned the elimination of the different internal component to component delays, the minimization of the global clocking resources and a strategic separation of the data path from the control part. Results: The working frequency of our design attained the 561 MHz, allowing 161786 scalar multiplications per second, outperforming one of the best state of the art implementations (555 MHz); the other contribution concerns the acceleration of the field inverse scheme with a frequency of 777.341 MHz. Conclusion: The results indicated that using different optimizations at the hardware level improve efficiently the acceleration of the ECC scalar multiplication and the choice of the target circuit gratefully enhances propagation delays and increases frequency.


© 2009 Mohamed Abdelkader Bencherif, Hamid Bessalah and Abderrezak Guessoum. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.