Design of Multi-Valued Quaternary Based Analog-to-Digital Converter
A.H.M. Zahirul Alam, Wahab Adetunji Lawal, Sheroz Khan and Muhammad Mahbubur Rashid
DOI : 10.3844/ajassp.2009.1521.1525
American Journal of Applied Sciences
Volume 6, Issue 8
Problem statement: The design of multi-valued quaternary based Analog-to-Digital Converter (ADC) circuit was presented. The ADC generates multi-valued logic outputs rather than the conventional binary output system to overall reduction in circuit complexity and size. Approach: Design was implemented using pipeline ADC architecture and was simulated using model parameters based on standard 0.13 µm CMOS process. Results: Performance analysis of the design showed desirable performance parameters in terms of response, low power consumption, and a sampling rate of 10 MHz at a supply voltage of 1.3V was achieved. Conclusion/Recommendations: The ADC design was suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple-valued logic design.
© 2009 A.H.M. Zahirul Alam, Wahab Adetunji Lawal, Sheroz Khan and Muhammad Mahbubur Rashid. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.