A New Efficient-Silicon Area MDAC Synapse
Zied Gafsi, Nejib Hassen, Mongia Mhiri and Kamel Besbes
DOI : 10.3844/ajassp.2007.378.385
American Journal of Applied Sciences
Volume 4, Issue 6
Using the binary representation Î£iDi2i in the Multiplier digital to analog converter (MDAC) synapse designs have crucial drawbacks. Silicon area of transistors, constituting the MDAC circuit, increases exponentially according to the number of bits. This latter is generated by geometric progression of common ratio equal to 2. To reduce this exponential increase to a linear growth, a new synapse named Arithmetic MDAC (AMDAC) is designed. It functions with a new representation based on arithmetic progressions. Using the AMS CMOS 0.35Î¼m technology the silicon area is reduced by a factor of 40%.
© 2007 Zied Gafsi, Nejib Hassen, Mongia Mhiri and Kamel Besbes. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.